New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss

The measured IDDQ current as a function of vectors is defined here as the IDDQ signature of a chip. We examined the IDDQ signatures of a large number of SEMATECH chips that have been classified us good or bud by a combined decision from functional, delay and scan tests. We find that a single IDDQ threshold, whether absolute or differential, cannot separate good/bud chips with any desirable accuracy, because the good chip signature can be any one of several well-defined graphs. In general, the signature of a good chip is found to contain discrete levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. Bused on observations, we develop a set of five graphical criteria, which provide lower defect level and yield loss compared to other non&D9 test methods. The reason is that the graphical procedure customizes the decision for the chip-under-test, and may substantially reduce the usage of other conventional tests.